There is a system which transmits and receives packetized cells. An example is shown in FIG. 16. A similar system is disclosed in the official gazette of Japanese Unexamined Patent Publication No. Hei-9-34816. A LAN 100 accommodating users using IP protocol are connected to a IP network 200 with encapsulation equipment 201.
From a received IP packet, LAN 100 generates an ATM (asynchronous transfer mode) cell, to encapsulate by adding LLC (logical link control) and SNAP (subnetwork access point). Such method of transmission is called “IP over ATM”.
In encapsulation equipment 201 in large-scale IP network 200, the aforementioned encapsulated IP packet is further encapsulated to a new capsule by adding an intranetwork header proper to the network for use only within the network. The intranetwork header is deleted at the time of transmission from IP network 200 to a user belonging to LAN 100 in encapsulation equipment 201.
In FIG. 17, there is shown an ATM cell format of AAL Type 5. (AAL: ATM adaptation layer; a layer in which the length of user application data from higher order layer is adjusted into integral multiples of an octet by padding or dividing.) An ATM cell consists of a 5-byte header and a 48-byte payload. The 5-byte header includes VCI (virtual channel identifier) and end cell indication flag PT0 of cells comprising a packet.
An IP packet is output from a user 102 using a cell format shown in FIG. 17. The IP packet consisting of ATM cells is encapsulated as shown in FIGS. 18A, 18B.
Namely, ATM cells are packetized so that the maximum frame length is 65,535 octets. A ‘PAD’ consisting of 1 to 47 bytes may be inserted so that the packet length becomes integral multiples of 48-byte. Further, an 8-byte trailer which includes user information, frame length and CRC (cyclic redundancy check) is added.
Each frame of the IP packet includes the above-mentioned 3-byte LLC and 5-byte SNAP as a result of encapsulation. In a concentrator 101 shown in FIG. 16, ATM cells encapsulated into an IP packet are multiplexed for a plurality of virtual channels (VC-multiplexed).
The VC-multiplexed ATM cells can be demultiplexed to separate a packet for respective VCs by referring VCI in ATM cell header and by detecting the last-cell flag PT0.
Encapsulation equipment 201 provides the following functions: terminating in AAL5 a packet cell received from user 102; identifying an outgoing route to overwrite a new VC; and adding an intranetwork header proper to IP network 200 to transmit to a connection server 202, as shown in FIG. 18B.
On the other hand, encapsulation equipment 201 provides functions of; terminating in AAL5 a packet received from connection server 202 in IP network 200; deleting the header proper to the network; and identifying a destination user 102 to overwrite a new VC to transmit to the destination user.
Here, there may be a case that packets to an identical user are simultaneously received from a plurality of routes in the large-scale IP network. In order to prevent packets from being mixed to produce packet loss, the cells are packetized before transmission to the user. Thus assigning an identical VC to packets from different routes to that destination can be avoided.
Note that in the case of a packet cell transmitted from a user to another user both accommodated in LAN 100, the above header proper to the network is neither added nor deleted.
In order to provide encapsulation equipment 201 with the aforementioned functions, it is necessary to provide a buffering function for packetizing and storing received data on a per cell basis.
In FIG. 19, there is shown an example of configuration block diagram of packet buffer equipment to realize above functions. According to packet buffer equipment shown in FIG. 19, a received packet is stored for saving in packet buffer memory 210. A header in the packet is read out and analyzed and a new header is added to transmit, using software or firmware.
Specifically, as shown in FIG. 19, a received packet is once stored in a packet buffer memory 210. The packet is then transferred through a DMA circuit 211 to packet buffer memory 210. Predetermined read-out and analysis of the packet header is performed in a CLAD (cell assembly & disassembly) 212. Then a header proper to the network is generated and added for encapsulation, and the packet is transmitted.
The execution of the above-mentioned process in CLAD 212 is controlled by a microprocessor 214 according to the firmware 213, or software, for header analysis and generation.
Here, at the time of executing the process in CLAD 212 by the firmware 213 or software controlled by a microprocessor 214, reduction of processing time is substantially difficult. This may produce such a bottleneck that the header addition process affects the limitation to line accommodation capability especially when high-speed multiplexing lines are used.
Therefore, in recent years, as transmission lines become higher in speed and larger equipment in capacity is required, it is needed to perform packet header analysis and generation with higher speed using hardware. In this case, however, it is required to perform packet header analysis and addition processing within a predetermined period, so that header analysis and addition processing may catch up with the packet flow.
When the time required for packet processing is not constant, it is necessary to prepare to buffer an appropriate amount of packets considering maximum processing delay.